Name Description
Processor A processor has so many definations, one of them is that it is a logic circuitry that responds to and processes the basic instructions that drive a computer. It is also called the brain of the computer as it controls the workings of all the hardware and software of the computer
Cache This is a small-sized type of volatile computer memory that proovides high-speed data access to aprocessor and stores frequently used computer programs, applications and data
Instruction Cycle This is the processing required for a single instruction
Program Counter(PC) Holds the address of the next instruction to be fetched
Instruction Register(IR) The fetched instruction is loaded into the instruction register
Accumulator Provides a temporary storage for an instruction
Memory Address Register(MAR) It holds the location of data that needs to be accessed or the address to which data will be sebt abd stored
Memory Data Register(MDR) it stores the data being transfered to and from the immediate access storage. It contains the copy of designated memory locations specified by the memory address register
Mapping Function When a new block of data is rerad into the cache, the Mapping Function determines which cache location the block will occupy.
Replacement Algorithm It chooses within the constraints of the mapping function, which block to replace when a new block is to be located into the cache and the cche already has all slots filled with othe blocks.
First In First Out(FIFO) A method for organizing and manipulating a data buffer, where the oldest(first) entry, or 'head' of the queue, is processed first
Least Recently Used An algorithm which in which the page that has recently been used will be replaced
Direct Mapping The simplest way of associating main memory blocks with cache blocks. In this technique, block k of main memory maps into block k module m of the cache, where m is the total number of blocks in cache.
Associative Mapping In this type of mapping the associative memory is used to store content and addresses both of the memory word. Any block can go into any line of the cache. This means that the word id bits are used to identify which word in the block is needed, but the tag becomes all of the remaining bits.
Set Associative Mapping A compromise between a direct mapped cache and a fully associative cache where each address is mapped to a certain set of cache locations. The address space is divided into blocks of 2^m bytes(the cache line size), discarding the bottom m address bits.